In this whitepaper, Mentor Graphics explain a top down approach to circuit design, using Verilog-A which encourages early system level simulations to verify interface and integration issues. Benefits include:
•Perform behavioural modelling for faster runtimes and early system level simulations
•Special measurements with DNL, INL, and relative settling time
•Create complex input stimuli
•Create models of non-standard devices such as MEMS, image sensors, or TFTs
The whitepaper reviews:
•Behaviour modelling and modelling development
•Simulation runtimes for a PLL
•Signal blocks modelling
•SOA checks